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Freescale Semiconductor /MKL82Z7 /SIM /SCGC5

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Interpret as SCGC5

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)LPTMR0 0 (0)SECREG 0 (0)LPTMR1 0 (0)TSI 0 (0)PTA 0 (0)PTB 0 (0)PTC 0 (0)PTD 0 (0)PTE 0 (0)EMVSIM0 0 (0)EMVSIM1 0 (0)LTC 0 (0)LPUART0 0 (0)LPUART1 0 (0)LPUART2 0 (0)QSPI0 0 (0)FLEXIO0

LPTMR0=0, PTA=0, TSI=0, EMVSIM0=0, PTE=0, FLEXIO0=0, LPTMR1=0, SECREG=0, LPUART0=0, PTB=0, QSPI0=0, LPUART2=0, PTD=0, LTC=0, PTC=0, LPUART1=0, EMVSIM1=0

Description

System Clock Gating Control Register 5

Fields

LPTMR0

LPTMR0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
SECREG

SECREG Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
LPTMR1

LPTMR1 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
TSI

TSI Access Control

0 (0): Access disabled

1 (1): Access enabled
PTA

PTA Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PTB

PTB Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PTC

PTC Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PTD

PTD Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PTE

PTE Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
EMVSIM0

EMVSIM0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
EMVSIM1

EMVSIM1 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
LTC

LTC Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
LPUART0

LPUART0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
LPUART1

LPUART1 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
LPUART2

LPUART2 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
QSPI0

QSPI0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
FLEXIO0

FLEXIO0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data